This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.

Discusses power-constrained mixed-time-criticality systems and why they are complex to design and verify Explains the concepts of predictability and composability and how they address the design and verification challenges of mixed-time-criticality systems Provides an overview of the requirements of memory controllers in power-constrained mixed-time-criticality systems and discusses why current memory controllers struggle to satisfy them Includes supplementary material: sn.pub/extras

Autorentext

Sven Goossens received his M.Sc. in Embedded Systems from the Eindhoven University of Technology in 2010. He worked as a researcher in the Electrical Engineering of the same university until 2011, and then started as a Ph.D. student, graduating in 2015. He is currently employed as a Hardware Architect at Intrinsic-ID. His research interests include mixed time-criticality systems, composability and SDRAM controllers. Karthik Chandrasekar earned his M.Sc. degree in Computer Engineering from TU Delft in the Netherlands in November 2009. In October 2014, he received his Ph.D. also from the same university. His research interests include SoC Architectures, DRAM memories & memory controllers, on-chip communication networks and performance & power modeling and analysis. He is currently employed as a Senior Architect at Nvidia.

Benny Akesson received his M.Sc. degree at Lund Institute of Technology, Sweden in 2005 and a Ph.D. from Eindhoven University of Technology, the Netherlands in 2010. Since then, he has been employed as a Researcher at Eindhoven University of Technology, Czech Technical University in Prague, and CISTER/INESC TEC Research Unit in Porto. Currently, he is working as a Research Fellow at TNO-ESI. His research interests include memory controller architectures, real-time scheduling, performance modeling, and performance virtualization. He has published more than 50 peer-reviewed conference papers and journal articles, as well as two books about memory controllers for real-time embedded systems.

Kees Goossens received his Ph.D. in Computer Science from the University of Edinburgh in 1993. He worked for Philips/NXP Research from 1995 to 2010 on networks-onchips for consumer electronics, where real-time performance, predictability, and costs are major constraints. He was part-time professor at Delft University from 2007 to 2010, and is now full professor at the Eindhoven University of Technology, where his research focuses on composable (virtualized), predictable (real-time), low-power embedded systems, supporting multiple models of computation. He published 4 books, 100+ papers, and 24 patents.

Inhalt

Introduction.- Reconfigurable Real-Time Memory Controller Architecture.- Memory Patterns.- Cycle-Accurate SDRAM Power Modeling.- Power/Performance Trade-Offs.- Conservative Open-Page Policy.- Reconfiguration.- Related Work.- Conclusions and Future Work.- Appendix A: ILP Problem Formation.- Appendix B: Memory Specifications.- Appendix C: Code Listings.- Appendix D: List of Acronyms.- Appendix E: List of Symbols.