This fourth volume of the landmark handbook focuses on the design, testing, and thermal management of 3D-integrated circuits, both from a technological and materials science perspective. Edited and authored by key contributors from top research institutions and high-tech companies, the first part of the book provides an overview of the latest developments in 3D chip design, including challenges and opportunities. The second part focuses on the test methods used to assess the quality and reliability of the 3D-integrated circuits, while the third and final part deals with thermal management and advanced cooling technologies and their integration.

Autorentext
Paul D. Franzon is currently the Cirrus Logic Distinguished Professor of Electrical and Computer Engineering and Director of Graduate programs in ECE at North Carolina State University. He earned his PhD from the University of Adelaide, Adelaide, Australia. He has also worked at AT&T Bell Laboratories, DSTO Australia, Australia Telecom and four companies he cofounded, Communica, LightSpin Technologies, Polymer Braille Inc. and Avago. His current interests include applying machine learning to EDA, building machine learning accelerators, neuromorphic computing, RFID, advanced packaging, 3DICs and secure chip design. He has lead several major efforts and published over 300 papers in these areas. In 1993 he received an NSF Young Investigators Award, in 2001 was selected to join the NCSU Academy of Outstanding Teachers, in 2003, selected as a Distinguished Alumni Professor, received the Alcoa Research Award in 2005, and the Board of Governors Teaching Award in 2014. He served with the Australian Army Reserve for 13 years as an Infantry Soldier and Officer. He is a Fellow of the IEEE. Erik Jan Marinissen is Principal Scientist at IMEC in Leuven, Belgium and part-time Visiting Researcher at Eindhoven University of Technology in the Netherlands. Prior to IMEC, he worked at NXP Semiconductors and Philips Research in Eindhoven, Nijmegen, and Sunnyvale (CA). His research on IC test and design-for-test covers topics as diverse as modular test of SoCs, 3D-stacked ICs, CMOS below 10nm, silicon photonics, and STT-MRAMs. Marinissen received the MSc degree in computing science and the PDEng degree in software technology from Eindhoven University of Technology. An IEEE Fellow, he is a co-author of more than 275 journal and conference papers and a co-inventor of 18 granted patent families. He served as editor-in-chief of IEEE Std 1500 and as founder/chair of the IEEE Std P1838 Working Group on 3D-SIC test access. In 2019-2021, he serves on the Board of Governors of IEEE Computer Society. Muhannad S. Bakir is a Professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology. He is a recipient of the 2018 IEEE Electronics Packaging Society (EPS) Exceptional Technical Achievement Award for contributions to 2.5D and 3D IC heterogeneous integration, with focus on interconnect technologies. He is also a recipient of the 2018 McKnight Foundation Technological Innovations in Neuroscience Award, 2013 Intel Early Career Faculty Honor Award, 2012 DARPA Young Faculty Award, and 2011 IEEE EPS Outstanding Young Engineer Award. He has published more than 200 journal and conference papers in the areas of 2.5D and 3D IC heterogeneous integration, power delivery, embedded cooling, photonic interconnects, and flexible interconnects. Dr. Bakir serves on the editorial board of IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT) and IEEE Transactions on Electron Devices (TED). He is a Distinguished Lecturer for IEEE EPS. Philip Garrou is a consultant and expert witness in the field of IC packaging materials and applications, prior to which he was Director of Technology and Business Development for Dow Chemicals' Electronic Materials business. He is author of the weekly blog 'Insights from the Leading Edge' (IFTLE) at www.3Dincites.com. Mitsumasa Koyanagi is Professor in the Graduate School of Engineering at Tohoku University, Japan. After his PhD he joined the Central Research Laboratory of Hitachi where he was engaged in the research on semiconductor memories. Afterwards he worked at the Xerox Palo Alto Research Center in California, USA, before he became Professor in the Research Center for Integrated Systems at Hiroshima University, Japan. Peter Ramm is Head of Strategic Projects at Fraunhofer EMFT in Munich, Germany. He received Physics and Dr. rer. nat. degrees from the University of Regensburg and subsequently worked for Siemens in their DRAM facility in Regensburg, where he was responsible for the overall process integration with focus on backend-of-line. In 1988 he joined Fraunhofer IFT (now EMFT), working mainly on integration technologies for innovative devices and heterogeneous systems including the development of 3D TSV processes. Peter Ramm is co-author of over 100 publications and 36 issued patents (US, EU, Japan). He is IEEE Senior Member, IMAPS Fellow and Life Member, and received the Technical Achievement Award For Pioneering Work on 3D IC Stacking and Integration from IMAPS. Peter Ramm is co-editor of Wiley-VCH's Handbook of Wafer Bonding and Encyclopedia on Materials, Science and Technology....

Inhalt

PART I: Design

01 3D Design Styles

02 Ultra-Fine Pitch 3D-Stacked Integrated Circuits: Technology, Design Enablement and Application

03 Power Delivery Network and Integrity in 3D IC Chips

04 Multiphysics Challenges and Solutions for Design of Heterogeneous 3D-Integrated Systems

05 Physical Design Flow for 3D/CoWoS Stacked ICs

06 Design and CAD Solutions for Cooling and Power Delivery for Monolithic 3D Ics

07 Electronic Design Automation for 3D

08 3D Stacked DRAM Memories

PART II: Test

09 Cost Modelling for 2.5D and 3D Stacked ICs

10 Interconnect Testing for 2.5D- and 3D-SICs

11 Pre-Bond Testing Through Direct Probing of Large-Array Fine-Pitch Micro-Bumps

12 3D Design-for-Test Architecture

13 Optimization of Test-Access Architectures and Test Scheduling for 3D ICs

14 IEEE P1838 3D Test Access Standard-in-Development

15 Test and Debug Strategy for TSMC CoWoS Stacking Process Based Heterogeneous 3D IC: A Silicon Study

PART III: Thermal Management

16 Thermal isolation and cooling technologies for heterogeneous 3-D and 2.5-D ICs

17 Passive and Active Thermal Technologies: Modeling and Evaluation

18 Thermal Modeling and Experimental Model Validation for 3D Stacked ICs

19 On the Thermal Management of 3D ICs: from back-side, to volumetric heat removal