Three-Dimensional Integrated Circuit Design

This book presents an overview of the field of 3D IC design, with an

emphasis on electronic design automation (EDA) tools and algorithms

that can enable the adoption of 3D ICs, and the architectural

implementation and potential for future 3D system design. The aim of

this book is to provide the reader with a complete understanding of:

• the promise of 3D ICs in building novel systems that enable the chip

industry to continue along the path of performance scaling,

• the state of the art in fabrication technologies for 3D integration,

• the most prominent 3D-specific EDA challenges, along with solutions

and best practices,

• the architectural benefits of using 3D technology,

• architectural-and system-level design issues, and

• the cost implications of 3D IC design.

Three Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures is intended for practitioners in the field, researchers and graduate students seeking to know more about 3D IC design.

Résumé
We live in a time of great change. In the electronics world, the last several decades have seen unprecedented growth and advancement, described by Moore's law. This observation stated that transistor density in integrated circuits doubles every 1. 52 years. This came with the simultaneous improvement of individual device perf- mance as well as the reduction of device power such that the total power of the resulting ICs remained under control. No trend remains constant forever, and this is unfortunately the case with Moore's law. The trouble began a number of years ago when CMOS devices were no longer able to proceed along the classical scaling trends. Key device parameters such as gate oxide thickness were simply no longer able to scale. As a result, device o- state currents began to creep up at an alarming rate. These continuing problems with classical scaling have led to a leveling off of IC clock speeds to the range of several GHz. Of course, chips can be clocked higher but the thermal issues become unmanageable. This has led to the recent trend toward microprocessors with mul- ple cores, each running at a few GHz at the most. The goal is to continue improving performance via parallelism by adding more and more cores instead of increasing speed. The challenge here is to ensure that general purpose codes can be ef?ciently parallelized. There is another potential solution to the problem of how to improve CMOS technology performance: three-dimensional integrated circuits (3D ICs).

Contenu
3D Process Technology Considerations.- Thermal and Power Delivery Challenges in 3D ICs.- Thermal-Aware 3D Floorplan.- Thermal-Aware 3D Placement.- Thermal Via Insertion and Thermally Aware Routing in 3D ICs.- Three-Dimensional Microprocessor Design.- Three-Dimensional Network-on-Chip Architecture.- PicoServer: Using 3D Stacking Technology to Build Energy Efficient Servers.- System-Level 3D IC Cost Analysis and Design Exploration.