With ongoing technology scaling high resolution in the voltage domain becomes increasingly troublesome. Time domain resolution, however, is continuously improving as digital circuits become faster in each new technology generation. Time-to-Digital Converters describes the fundamentals of time-to-digital converters (TDC) based on analog and digital conversion principles. An in depth theoretical investigation is provided with respect to quantization, linearity, noise, and variability. Advanced TDC architectures are described that address the challenges of signed time interval measurement, long measurement time, high resolution, high linearity, low-power, variability and calibration, low mismatch among multiple measurements, and suitability for design automation. Resolution enhancement techniques such as pulse-shrinking, Vernier delay-line, local passive interpolation, gated delay-lines, and time amplification are introduced and discussed with respect to operating principle, resolution, power, area, conversion time, susceptibility to variations, and suitability for implementation and mass production. Finally, an overview on TDC applications in phase-locked-loops and analog-to-digital converters is given. Time-to-Digital Converters provides a strong theoretical basis and comprises a unique in depth overview on TDC architectures and conversion principles.

Résumé
Micro-electronics and so integrated circuit design are heavily driven by technology scaling. The main engine of scaling is an increased system performance at reduced manufacturing cost (per system). In most systems digital circuits dominate with respect to die area and functional complexity. Digital building blocks take full - vantage of reduced device geometries in terms of area, power per functionality, and switching speed. On the other hand, analog circuits rely not on the fast transition speed between a few discrete states but fairly on the actual shape of the trans- tor characteristic. Technology scaling continuously degrades these characteristics with respect to analog performance parameters like output resistance or intrinsic gain. Below the 100 nm technology node the design of analog and mixed-signal circuits becomes perceptibly more dif cult. This is particularly true for low supply voltages near to 1V or below. The result is not only an increased design effort but also a growing power consumption. The area shrinks considerably less than p- dicted by the digital scaling factor. Obviously, both effects are contradictory to the original goal of scaling. However, digital circuits become faster, smaller, and less power hungry. The fast switching transitions reduce the susceptibility to noise, e. g. icker noise in the transistors. There are also a few drawbacks like the generation of power supply noise or the lack of power supply rejection.

Contenu
Foreword.- Time-to-Digital Converter Basics.- Theory of TDC Operation.- Advanced TDC Design Issues.- Time-to-Digital Converters with Sub-Gatedelay Resolution #x2013; The Third Generation.- Applications for Time-to-Digital Converters.