Adaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling

This book offers the first comprehensive coverage of digital design techniques to expand the power-performance tradeoff well beyond that allowed by conventional wide voltage scaling. Compared to conventional fixed designs, the approach described in this book makes digital circuits more versatile and adaptive, allowing simultaneous optimization at both ends of the power-performance spectrum. Drop-in solutions for fully automated and low-effort design based on commercial CAD tools are discussed extensively for processors, accelerators and on-chip memories, and are applicable to prominent applications (e.g., IoT, AI, wearables, biomedical). Through the higher power-performance versatility techniques described in this book, readers are enabled to reduce the design effort through reuse of the same digital design instance, across a wide range of applications. All concepts the authors discuss are demonstrated by dedicated testchip designs and experimental results. To make the results immediately usable by the reader, all the scripts necessary to create automated design flows based on commercial tools are provided and explained.

• Provides extensive coverage of the challenges and the key technologies enabling wide power-performance range in digital sub-systems (e.g., processors, memories, accelerators);
• Includes in-depth description of silicon-proven methodologies to design reconfigurable data path and clock path;
• Describes techniques for reconfigurable microarchitectures, down to the pipestage and the clock repeater level;
• Uses a highly interdisciplinary approach covering the circuit, the microarchitectural and the system levels of abstraction;
• Presents practical design examples and the related methodologies;
• Offers complementary design files and scripts, useful to replicate the presented developments and develop new designs.

Auteur

Saurabh Jain received the bachelor's and master's degrees from Indian Institute of Technology, Kanpur, India, in 2012 and 2013 respectively, the Ph.D. degree from National University of Singapore, Singapore, in 2018. After his Ph.D. he worked as a postdoctoral research fellow at the Department of Electrical and Computer Engineering of the National University of Singapore. Currently he is working as a research scientist at the processor architecture research lab (PARL) at Intel Labs, Bangalore.

His research interest includes development of reconfigurable architectures for widely voltage-scalable memory and logic and general purpose compute-in-memory.

Longyang Lin received the dual bachelor's degrees from Shenzhen University, Shenzhen, China and Umeå University, Umeå, Sweden, in 2011 and the master's degree from Lund University, Lund, Sweden, in 2013, and the Ph.D. degree from the National University of Singapore, Singapore, in 2018. He is currently a postdoctoral research fellow at the Department of Electrical and Computer Engineering of the National University of Singapore.

His research interests include ultra-low power VLSI circuits, self-powered sensor nodes, widely energy-scalable VLSI circuits and general purpose compute-in-memory.

Massimo Alioto received the Laurea (MSc) degree in Electronics Engineering and the Ph.D. degree in Electrical Engineering from the University of Catania (Italy) in 1997 and 2001, and the Bachelor of Music in Jazz Studies from the Conservatory of Music of Bologna in 2007. He is with the Department of Electrical and Computer Engineering, National University of Singapore where he leads the Green IC group and is the Director of the Integrated Circuits and Embedded Systems area. Previously, he held positions at the University of Siena, Intel Labs CRL (2013), University of Michigan Ann Arbor (2011-2012), BWRC University of California, Berkeley (2009-2011), and EPFL (Switzerland, 2007).

He has authored or co-authored more than 280 publications on journals and conference proceedings. He is co-author of four books, including Enabling the Internet of Things - from Circuits to Systems (Springer, 2017), Flip-Flop Design in Nanometer CMOS - from High Speed to Low Energy (Springer, 2015), and Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits (Springer, 2005). His primary research interests include self-powered wireless integrated systems, near-threshold circuits for green computing, widely energy- scalable and energy-quality scalable integrated systems, data-driven integrated systems, hardware-level security, and emerging technologies, among the others. He is the Editor in Chief of the IEEE Transactions on VLSI Systems (2019-2020), and was the Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2018). In 2009-2010 he was Distinguished Lecturer of the IEEE Circuits and Systems Society, for which he is/was also member of the Board of Governors (2015-2020), and Chair of the VLSI Systems and Applications Technical Committee (2010-2012). In the last five years, he has given 50+ invited talks in top conferences, universities and leading semiconductor companies. His research has been mentioned in more than 60 press releases and popular science articles in the last two years. He served as Guest Editor of several IEEE journal special issues (e.g., TCAS-I, TCAS-II, JETCAS). He also serves or has served as Associate Editor of a number of IEEE and ACM journals. He is/was Technical Program Chair (ISCAS 2023, SOCC, ICECS, NEWCAS, VARI, ICM, PRIME) and Track Chair in a number of conferences (ICCD, ISCAS, ICECS, VLSI-SoC, APCCAS, ICM). Currently, he is also in the IEEE Digital Architectures and Systems ISSCC subcommittee, and the IEEE ASSCC technical program committee. Prof. Alioto is an IEEE Fellow.

Contenu
PREFACEABOUT THE AUTHORSACKNOWLEDGEMENTS1. INTRODUCTION2. RECONFIGURABLE MICROARCHITECTURES DOWN TO PIPESTAGE AND MEMORY BANK LEVEL3. AUTOMATED DESIGN FLOW AND RUN-TIME OPTIMIZATION FOR RECONFIGURABLE MICROARCHITECTURES 4. CASE STUDIES OF RECONFIGURABLE MICROARCHITECTURES: ACCELERATORS, MICROPROCESSOR AND MEMORIES5. RECONFIGURABLE CLOCK NETWORKS, AUTOMATED DESIGN FLOWS, RUN-TIME OPTIMIZATION AND CASE STUDY 6. CONCLUSIONSAPPENDIX