Power Aware Computing

With the advent of portable and autonomous computing systems, power con­ sumption has emerged as a focal point in many research projects, commercial systems and DoD platforms. One current research initiative, which drew much attention to this area, is the Power Aware Computing and Communications (PAC/C) program sponsored by DARPA. Many of the chapters in this book include results from work that have been supported by the PACIC program. The performance of computer systems has been tremendously improving while the size and weight of such systems has been constantly shrinking. The capacities of batteries relative to their sizes and weights has been also improv­ ing but at a rate which is much slower than the rate of improvement in computer performance and the rate of shrinking in computer sizes. The relation between the power consumption of a computer system and it performance and size is a complex one which is very much dependent on the specific system and the technology used to build that system. We do not need a complex argument, however, to be convinced that energy and power, which is the rate of energy consumption, are becoming critical components in computer systems in gen­ eral, and portable and autonomous systems, in particular. Most of the early research on power consumption in computer systems ad­ dressed the issue of minimizing power in a given platform, which usually translates into minimizing energy consumption, and thus, longer battery life.

Contenu

List of Figures. List of Tables. Preface. Part I: 1. Comparative Analysis of Flip-Flops and Application of Data-Gating in Dynamic Flip-Flops for High Speed, Low Active and Low Leakage Power Dissipation; V. Srikantam, M. Martinez. 2. Low Power Sandwich/Spin Tunneling Memory Device; J. Daughton, et al. Part II: 3. Power-Efficient Issue Queue Design; A. Buyuktosunoglu, et al. 4. Micro-architecture Design and Control Speculation for Energy Reduction; D. Grunwald. 5. Energy-Exposed Instruction Sets; K. Asanovic, et al. Part III: 6. Dynamic Management of Power Consumption; T. Simunic. 7. Power Management Points in Power-Aware Real-Time Systems; R. Melhem, et al. 8. A Power-Aware API for Embedded and Portable Systems; C. Pereira, et al. Part IV: 9. PACT HDL: A Compiler Targeting ASICs and FPGAs with Power and Performance Optimizations; A. Jones, et al. 10. Compiler Optimizations for Low Power Systems; M. Kandemir, et al. 11. Power-Performance Trade-Offs in Second Level Memory Used by an ARM-like RISC Architecture; K. Puttaswamy, et al. Part V: 12. Application-Level Power Awareness; J.A. Barnett. 13. A Power-Aware, Satellite-Based Parallel Signal Processing Scheme; P.M. Shriver, et al. 14. The Case for Power Management in Web Servers; P. Bohrer, et al. Part VI: 15. Et2: A Metric for Time and Energy Efficiency of Computation; A.J. Martin, et al. 16. Challenges for Architectural Level Power Modeling; Nam Sung Kim, et al. 17. Software Energy Profiling; A. Sinha, A. Chandrakasan. Index.