Datamining and Diagnosing Integrated Circuit Fails addresses the problem of obtaining maximum information from (functional) Integrated Circuit fail data about the defects that caused the fails. It starts at the highest level from mere sort codes, and drills down via various data mining techniques to detailed logic diagnosis. The various approaches discussed in this book have a thorough theoretical underpinning, but are geared towards applications on real life fail data and state of the art ICs. This book brings together a large number of analysis techniques that are suitable for IC fail data, but that are not available elsewhere in a single place. Several of the techniques, in fact, have been presented only recently in technical conferences.

Datamining and Diagnosing Integrated Circuit Fails begins with a discussion of sort codes and yield analysis. It then discusses various data mining techniques centered on fail syndrome commonalities and the statistics of embedded object fails. It gives a thorough discussion of the area dependence of the yield and of the recognition of spatial patterns of failing die or embedded objects. Next, it gives a detailed analysis of the relationship between defect coverage and yield. It ends with a description of state of the art logic diagnosis techniques.

The purpose of the book is to bring together in one place a large number of analysis, data mining and diagnosis techniques that have proven to be useful in analyzing IC fails. The descriptions of the techniques and analysis routines is sufficiently detailed that profession manufacturing engineers can implement them in their own work environment. There are many techniques for analyzing IC fails, but they are scattered over the professional IC test and diagnosis literature, and in various statistics and data mining handbooks. Moreover, many data mining techniques that are standard in other data analysis environments, and that are appropriate for analyzing IC fails, have not yet been employed for that purpose. There is a clear need for a single source for all these analysis techniques, suitable for professional IC manufacturing and test engineers.

Résumé
This book grew out of an attempt to describe a variety of tools that were developed over a period of years in IBM to analyze Integrated Circuit fail data. The selection presented in this book focuses on those tools that have a significant statistical or datamining component. The danger of describing sta tistical analysis methods is the amount of non-trivial mathematics that is involved and that tends to obscure the usually straigthforward analysis ideas. This book is, therefore, divided into two roughly equal parts. The first part contains the description of the various analysis techniques and focuses on ideas and experimental results. The second part contains all the mathematical details that are necessary to prove the validity of the analysis techniques, the existence of solutions to the problems that those techniques engender, and the correctness of several properties that were assumed in the first part. Those who are interested only in using the analysis techniques themselves can skip the second part, but that part is important, if only to understand what is being done.

Contenu

Introduction.- Statistics.- Yield Statistics.- Area Dependence of the Yield.- Statistics of Embedded Object Fails.- Fail Commonalities.- Spatial Patterns.- Test Coverage and Test Fallout.- Logic Diagnosis.- Slat Based Diagnosis.- Data Collection Requirements.- Appendix A. Distribution of IC Fails.- Appendix B. General Yield Model.- Appendix C. Simplified Center-Satellite Model.- Appendix D. Quadrat Analysis.- Appendix E. Cell Fail Probabilities.- Appendix F. Characterization Group.- Appendix G. Component Fail Probabilities.- Appendix H. Yield and Coverage.- Appendix I. Estimating First Fail Probabilities from the Fallout.- Appendix J. Identity of M and S.- References.- Index.