Nowdays GaN HEMT technology reached maturity level that allows industral fabrication of such devices for wide range of civil (telecommunications, power electrinics, automotive etc.), as well as space and military (phased array radars) applications. At this level, technology start reaching physical limits of GaN material and require new approaches that will allow to overcome some of well known problems related to GaN HEMTs, such as high gate leakage currents, reliability issues and difficulties of normally-off transistor fabrication.  The goal of these theses is theoretical and experimental confirmation of the idea, that using peizoelectric nature of GaN crystal will allow local modification of GaN HEMT channel by means of external mechanical stress (using first and second passivation layers as stressors).  After implementation of the proposed technology changes and new device geometry in process flow intended for 150 nm GaN HEMT MMIC fabrication, E/D devices with pinch-off voltages +0.1V and -1.65V respectively were fabricated on the same wafer within single process flow. It was observed, that E-mode devices, fabricated using compressed passivation layers, demonstrate lower gate leakage currents and more robust in HTRB test as compared to D-mode devices. In summary, it was demonstrated, that it is possible to control pinch-off voltage and gate leakage current of short channel GaN HEMTs by application of external stress. Usage of external stress, opens new degree of freedom in device optimization, and extends opportunities for more advanced MMIC design.