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Edited by key figures in 3D integration and written by top authors from high-tech companies and renowned research institutions, this book covers the intricate details of 3D process technology.
As such, the main focus is on silicon via formation, bonding and debonding, thinning, via reveal and backside processing, both from a technological and a materials science perspective. The last part of the book is concerned with assessing and enhancing the reliability of the 3D integrated devices, which is a prerequisite for the large-scale implementation of this emerging technology.
Invaluable reading for materials scientists, semiconductor physicists, and those working in the semiconductor industry, as well as IT and electrical engineers.
Auteur
Philip Garrou is a consultant and expert witness in the field of IC packaging materials and applications, prior to which he was Dir. of Technology and Business Dev. for Dow Chemicals' Electronic Materials business. Dr. Garrou is a Fellow of IEEE and IMAPS and served as President of the IEEE CPMT Society and IMAPS. He has co-authored 3 microelectronics texts and 100+ publications. He is Assoc. Ed. and author of the weekly blog "Insights from the Leading Edge" for Solid State Technology and has co-authored 3DIC reports for both TechSearch and Yole.
Mitsumasa Koyanagi is Professor in the Graduate School of Engineering at Tohoku University, Japan. After his PhD in electrical engineering he joined the Central Research Laboratory of Hitachi where he was engaged in the research on semiconductor memories. After a three-year stay at the Xerox Palo Alto Research Center in California, USA, he became Professor in the Research Center for Integrated Systems at Hiroshima University, Japan. Mitsumasa Koyanagi received numerous awards, including the Solid-State Devices and Materials Award.
Peter Ramm is head of the department Heterogeneous System Integration of Fraunhofer EMFT in Munich, Germany, where he is responsible for the key competence "Si Processes, Device and 3D Integration". He received the physics and Dr. rer. nat. degrees from the University of Regensburg and subsequently worked for Siemens in the DRAM facility where he was responsible for the process integration. In 1988 he joined Fraunhofer IFT in Munich, focusing for more than 25 years on 3D integration technologies. Peter Ramm is co-author of over 100 publications and 24 patents and editor of Wiley's "Handbook of Wafer Bonding". He received the "Ashman Award 2009" from IMAPS "For Pioneering Work on 3D IC Stacking and Integration".
Contenu
List of Contributors xvii
1 3D IC Integration Since 2008 1
Philip Garrou, Peter Ramm, and Mitsumasa Koyanagi
1.1 3D IC Nomenclature 1
1.2 Process Standardization 2
1.3 The Introduction of Interposers (2.5D) 4
1.4 The Foundries 6
1.4.1 TSMC 6
1.4.2 UMC 7
1.4.3 GlobalFoundries 7
1.5 Memory 7
1.5.1 Samsung 7
1.5.2 Micron 8
1.5.3 Hynix 9
1.6 The Assembly and Test Houses 9
1.7 3D IC Application Roadmaps 10
References 11
2 Key Applications and Market Trends for 3D Integration and Interposer Technologies 13
Rozalia Beica, Jean-Christophe Eloy, and Peter Ramm
2.1 Introduction 13
2.2 Advanced Packaging Importance in the Semiconductor Industry is Growing 16
2.3 3D Integration-Focused Activities The Global IP Landscape 18
2.4 Applications, Technology, and Market Trends 22
References 32
3 Economic Drivers and Impediments for 2.5D/3D Integration 33
Philip Garrou
3.1 3D Performance Advantages 33
3.2 The Economics of Scaling 33
3.3 The Cost of Future Scaling 34
3.4 Cost Remains the Impediment to 2.5D and 3D Product Introduction 37
3.4.1 Required Economics for Interposer Use in Mobile Products 38
3.4.2 Silicon Interposer Pricing 38
References 40
4 Interposer Technology 41
Venky Sundaram and Rao R. Tummala
4.1 Definition of 2.5D Interposers 41
4.2 Interposer Drivers and Need 42
4.3 Comparison of Interposer Materials 44
4.4 Silicon Interposers with TSV 45
4.5 Lower Cost Interposers 48
4.5.1 Glass Interposers 48
4.5.1.1 Challenges in Glass Interposers 49
4.5.1.2 Small-Pitch Through-Package Via Hole Formation and Ultrathin Glass Handling 49
4.5.1.3 Metallization of Glass TPV 51
4.5.1.4 Reliability of Copper TPVs in Glass Interposers 52
4.5.1.5 Thermal Dissipation of Glass 53
4.5.1.6 Glass Interposer Fabrication with TPV and RDL 53
4.5.2 Low-CTE Organic Interposers 53
4.5.3 Polycrystalline Silicon Interposer 55
4.5.3.1 Polycrystalline Silicon Interposer Fabrication Process 56
4.6 Interposer Technical and Manufacturing Challenges 57
4.7 Interposer Application Examples 58
4.8 Conclusions 60
References 61
5 TSV Formation Overview 65
Dean Malta
5.1 Introduction 65
5.2 TSV Process Approaches 67
5.2.1 TSV-Middle Approach 68
5.2.2 Backside TSV-Last Approach 68
5.2.3 Front-Side TSV-Last Approach 69
5.3 TSV Fabrication Steps 70
5.3.1 TSV Etching 70
5.3.2 TSV Insulation 71
5.3.3 TSV Metallization 71
5.3.4 Overburden Removal by CMP 72
5.3.5 TSV Anneal 73
5.3.6 Temporary Carrier Wafer Bonding and Debonding 74
5.3.7 Wafer Thinning and TSV Reveal 74
5.4 Yield and Reliability 75
References 76
6 TSV Unit Processes and Integration 79
Sesh Ramaswami
6.1 Introduction 79
6.2 TSV Process Overview 80
6.3 TSV Unit Processes 82
6.3.1 Etching 82
6.3.2 Insulator Deposition with CVD 83
6.3.3 Metal Liner/Barrier Deposition with PVD 84
6.3.4 Via Filling by ECD of Copper 84
6.3.5 CMP of Copper 85
6.3.6 Temporary Bonding between Carrier and Device Wafer 86
6.3.7 Wafer Backside Thinning 86
6.3.8 Backside RDL 87
6.3.9 Metrology, Inspection, and Defect Review 87
6.4 Integration and Co-optimization of Unit Processes in Via Formation Sequence 88
6.5 Co-optimization of Unit Processes in Backside Processing and Via-Reveal Flow 89 6.6 Integration an...