Computer Organization, Design and Architecture

Auteur

Dr. Sajjan G. Shiva joined the University of Memphis in 2002 as the Director of the Computer Science Division and transitioned it into the Department of Computer Science in 2005. He served as the Founding Chair through 2015. He has served on the computer science faculty at the University of Alabama in Huntsville and Alabama A&M University. He has also served as the Manager of Software Quality Assurance at Teledyne Brown Engineering; Senior Software Engineer and Executive Manager (Technical) at Intergraph Corporation; and Technical Advisor, Computer Technologies Division, U.S. Army Space and Strategic Defense Command. Dr. Shiva has consulted with industry and government organizations in the areas of software engineering, computer architecture, artificial intelligence, and expert systems. He is a Fellow of IEEE and a life member of ACM. He has received research funding from NSF, NASA, U.S. Department of Defense, and ONR. His current interests are game theoretic cyber security and secure software engineering.

Texte du rabat

This unique and classroom-proven text provides a hands-on introduction to the design of computer systems. It depicts, step by step, the design and programming of a simple but complete hypothetical computer, followed by detailed architectural features of existing computer systems as enhancements to the structure of the simple computer.

Contenu

1. Introduction. 2. Number Systems and Codes. 3. Combinational Logic. 4. Sequential Logic. 5. A Simple Computer: Organization and Programming. 6. A Simple Computer: Hardware Design. 7. Input/Output. 8. Processor and Instruction Set Architectures. 9. Memory and Storage. 10. Arithmetic/Logic Unit Enhancement. 11. Control Unit Enhancement. 12. Advanced Architectures. 13. Embedded Systems. 14. Mobile Processors and System on Chip. 15. Computer Networks and Distributed Processing. 16. Performance Evaluation Appendix A: Details of Representative Integrated Circuit Appendix B: Stack Implementation Appendix C: ARM Instruction Set Architecture Appendix D; RISC-V Instruction Set Architecture