Structural Decision Diagrams in Digital Test

This is the first book that sums up test-related modeling of digital circuits and systems by a new structural-decision-diagrams model. The model represents structural and functional information jointly and opens a new area of research.

The book introduces and discusses applications of two types of structural decision diagrams (DDs): low-level, structurally synthesized binary DDs (SSBDDs) and high-level DDs (HLDDs) that enable diagnostic modeling of complex digital circuits and systems.

Topics and features:

• Provides the definition, properties and techniques for synthesis, compression and optimization of SSBDDs and HLDDs
• Provides numerous working examples that illustrate the key points of the text
• Describes applications of SSBDDs and HLDDs for various electronic design automation (EDA) tasks, such as logic-level fault modeling and simulation, multi-valued simulation, timing-critical path identification, and test generation
• Discusses the advantages of the proposed model to traditional binary decision diagrams and other traditional design representations

• Combines SSBDDs with HLDDs for multi-level representation of digital systems for enabling hierarchical and cross-level solving of complex test-related tasks This unique book is aimed at researchers working in the fields of computer science and computer engineering, focusing on test, diagnosis and dependability of digital systems. It can also serve as a reference for graduate- and advanced undergraduate-level computer engineering and electronics courses.

  Three authors are affiliated with the Dept. of Computer Systems at the Tallinn University of Technology, Estonia: Raimund Ubar is a retired Professor, Jaan Raik and Maksim Jenihhin are tenured Professors. Artur Jutman , PhD, is a researcher at the same university and the CEO of Testonica Lab Ltd., Estonia.

Proposes a new type of structural decision diagrams Valid for a vast array of applications in the field of digital test Covers speed-up of fault simulation, as well as test generation avoiding mutual masking of multiple faults

Auteur

Prof. Emeritus Raimund Ubar is a professor emeritus at the Department of Computer Systems of Tallinn University of Technology, Estonia. He received his Ph.D. degree at Bauman Moscow State Technical University in 1971, and DSc degree at Latvian Academy of Sciences in 1986. He has been with TU Tallinn since 1971, Head of the Computer Department (1987-1992), Head and Founder of the Electronics Competence Center (1993-1996), and Head of the Estonian Research Centre for Integrated Electronic Systems and Biomedical Engineering (2007-2015). He has published more than 500 peer-reviewed scientific papers and 5 books and supervised 20 PhDs. His research interests cover a wide area in electrical engineering and computer science domains, including digital design and test, fault modeling and diagnosis, design for testability, as well as fault tolerance and built-in self-test. He has lectured and given courses at more than 20 universities, served as General Chair for the European Test Conference, and other conferences such as NORCHIP, BEC, EWDTC. He is a member of Estonian Academy of Sciences, Life Senior Member of IEEE, Golden Core member of IEEE Computer Society, and honored professor of Ukrainian State University of Radioelectronics. He was awarded from Estonian Government by White Cross Orden of III Class, by National Award for Long-term Successful R&D, and by several Meritorious Service Awards of the IEEE Computer Society.

Recent books:

1. R.Ubar, A.Jasnetski, A.Tsertov, A.S.Oyeniran. Software-Based Self-Test with Decision Diagrams for Microprocessors. Lambert Academic Publishing, 2018, 171 p.

2. R.Ubar, J.Raik, H.-T.Vierhaus (Eds). Design and Test Technology for Dependable Systems-on-Chip. IGI Global, 2011, 550 p.

3. O.Novak, E.Gramatova, R.Ubar. Handbook of Electronic Testing. CTU Printhouse, Prague, 2005, 400 p

Prof. Jaan Raik is a professor of digital systems' verification at the Department of Computer Systems and the head of the Centre for Dependable Computing Systems of Tallinn University of Technology (TalTech), Estonia. Prof. Raik received his M.Sc. and Ph.D. degrees at TalTech in 1997 and in 2001, respectively. He has co-authored more than 200 peer-reviewed scientific publications. His research interests cover a wide area in electrical engineering and computer science domains, including hardware test, functional verification, fault-tolerance and security as well as emerging computer architectures. He is a member of IEEE Computer Society, HiPEAC and a member of steering/program committees of several leading conferences in his fields. He acted as the General Co-Chair of IEEE European Test Symposium 2020, the General Chair of the IFIP/IEEE VLSI-SoC'16 and IEEE DDECS'12 Conferences and the Program Co-Chair of IEEE DDECS'23, CDN-Live'16 and the Program Chair of IEEE DDECS'15. He was the main coordinator for several Europe-wide research and collaboration actions. 16 PhD Theses have been successfully defended under his supervision.

Prof. Maksim Jenihhin is a tenured associate professor of Computing Systems Reliability at the Department of Computer Systems of Tallinn University of Technology and the head of the research group "Trustworthy and Efficient Computing Hardware". He received his Ph.D. degree in Computer Engineering from the same university in 2008. His research interests include methodologies and EDA tools for hardware design, verification and debugging as well as nanoelectronics reliability and manufacturing test topics. He supervised 5 PhD theses on these topics and published more than 170 peer-reviewed publications. He is a coordinator for national and European research projects, including H2020 MSCA ITN "RESCUE - Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems Design", PRG 2022 "CRASHLESS- Cross-Layer Reliability and Self-Health Awareness for Intelligent Autonomous Systems". Prof. Jenihhin is a member of executive and program committees for IEEE ETS, DATE, DDECS, and a number of other international events and served as a guest editor for special issues of journals.

Dr. Artur Jutman has been managing industrial and research projects in Testonica Lab Ltd. for over 15 years now. His professional focus embraces such topics as diagnostic and defect modeling, test optimization, embedded test instrumentation, test firmware, BIST, DFT as well as both ASIC and system test in a broad sense - all yielding over 160 peer-reviewed research papers published. Dr. Jutman has co-ordinated several EU-funded research projects on test-related topics, participated in organizing test conferences and workshops across Europe as well as given several keynotes, invited talks, embedded and full tutorials at international conferences and symposia. Being deeply inspired by test technologies, Artur has given numerous hands-on training sessions and lecture courses in testing, diagnostics, and DFT for industrial engineers and graduate students in several countries, incl. Germany, Italy, Sweden, Portugal, Russia, and Estonia. Before starting his industrial career, Dr. Jutman spent cumulatively several years being a visiting researcher in several universities across Europe, incl. TU Darmstadt, TU Ilmenau, TU Warsaw, TU Jonkoping, Politecnico di Torino, University of Aveiro, and University of Linkoping. He is also a member of the executive committee of the Nordic Test Forum (NTF) society. Dr. Artur Jutman received his M.Sc. and Ph.D. degrees in computer engineering from Tallinn University of Technology, Estonia in 1999 and 2004 respectively.

Contenu

Chapter 1: Introduction.- Chapter 2: Overview of structural decision diagrams.- Chapter 3: Structurally Synthesized Binary Decision Diagrams.- Chapter 4: Fault modeling in digital circuits.- Chapter 5: Logic-level fa…