Advanced Memory Optimization Techniques for Low-Power Embedded Processors

In a relatively short span of time, computers have evolved from huge mainframes to small and elegant desktop computers, and now to low-power, ultra-portable handheld devices. Witheachpassinggeneration,computersconsistingofprocessors,memoriesandperipherals becamesmallerandfaster.Forexample,the?rstcommercialcomputerUNIVACIcosted $1 million dollars, occupied 943 cubic feet space and could perform 1,905 operations per second [94]. Now, a processor present in an electric shaver easily outperforms the early mainframe computers. The miniaturization is largely due to the efforts of engineers and scientists that made the expeditious progress in the microelectronic technologies possible. According to Moore's Law [90], the advances in technology allow us to double the number of transistors on a single silicon chip every 18 months. This has lead to an exponential increase in the number of transistors on a chip, from 2,300 in an Intel 4004 to 42 millions in Intel Itanium processor [55]. Moore's Law has withstood for 40 years and is predicted to remain valid for at least another decade [91]. Notonlytheminiaturizationanddramaticperformanceimprovementbutalsothesign- icantdropinthepriceofprocessors,hasleadtosituationwheretheyarebeingintegratedinto products, such as cars, televisions and phones which are not usually associated with c- puters.This new trend has also been called the disappearing computer, where the computer does not actually disappear but it is everywhere [85]. Digital devices containing processors now constitute a major part of our daily lives. Asmalllistofsuchdevicesincludesmicrowaveovens,televisionsets,mobilephones,digital cameras, MP3 players and cars. Whenever a system comprises of information processingdigitaldevicestocontrolortoaugmentitsfunctionality,suchasystemistermedanembedded system. Therefore, all the above listed devices can be also classi?ed as embedded systems.

The complete application, including data variables and code segments, is optimized Comprehensive architecture-level exploration for real-life applications Demonstration of architecture-aware compilation techniques

Auteur
Prof. Peter Marwedel has published numerous books with Springer

Texte du rabat

The design of embedded systems warrants a new perspective because of the following two reasons: Firstly, slow and energy inefficient memory hierarchies have already become the bottleneck of the embedded systems. It is documented in the literature as the memory wall problem. Secondly, the software running on the contemporary embedded devices is becoming increasingly complex. It is also well understood that no silver bullet exists to solve the memory wall problem. Therefore, this book explores a collaborative approach by proposing novel memory hierarchies and software optimization techniques for the optimal utilization of these memory hierarchies. Linking memory architecture design with memory-architecture aware compilation results in fast, energy-efficient and timing predictable memory accesses.

The evaluation of the optimization techniques using real-life benchmarks for a single processor system, a multiprocessor system-on-chip (SoC) and for a digital signal processor system, reports significant reductions in the energy consumption and performance improvement of these systems. The book presents a wide range of optimizations, progressively increasing in the complexity of analysis and of memory hierarchies. The final chapter covers optimization techniques for applications consisting of multiple processes found in most modern embedded devices.

Advanced Memory Optimization Techniques for Low Power Embedded Processors is designed for researchers, complier writers and embedded system designers / architects who wish to optimize the energy and performance characteristics of the memory subsystem.

Contenu
Related Work.- Memory Aware Compilation and Simulation Framework.- Non-Overlayed Scratchpad Allocation Approaches for Main/Scratchpad Memory Hierarchy.- Non-Overlayed Scratchpad Allocation Approaches for Main/Scratchpad + Cache Memory Hierarchy.- Scratchpad Overlay Approaches for Main/Scratchpad Memory Hierarchy.- Data Partitioning and Loop Nest Splitting.- Scratchpad Sharing Strategies for Multiprocess Applications.- Conclusions and Future Directions.