Nano-CMOS and Post-CMOS Electronics

Texte du rabat

Over two volumes this work describes the modelling, design, and implementation of nano-scaled CMOS electronics, and the new generation of post-CMOS devices, at both the device and circuit levels.

Contenu

• Chapter 1: Self-healing analog/RF circuits
• Chapter 2: On-chip gate delay variability measurement in scaled technology node
• Chapter 3: Nanoscale FinFET devices for PVT-aware SRAM
• Chapter 4: Data stability and write ability enhancement techniques for FinFET SRAM circuits
• Chapter 5: Low-leakage techniques for nanoscale CMOS circuits
• Chapter 6: Thermal effects in carbon nanotube VLSI interconnects
• Chapter 7: Lumped electro-thermal modeling and analysis of carbon nanotube interconnects
• Chapter 8: High-level synthesis of digital integrated circuits in the nanoscale mobile electronics era
• Chapter 9: SPICEless RTL design optimization of nanoelectronic digital integrated circuits
• Chapter 10: Green on-chip inductors for three-dimensional integrated circuits: concepts, algorithms and applications
• Chapter 11: 3D NoC: a promising alternative for tomorrow's nanosystem design
• Chapter 12: A new paradigm towards performance centric computation beyond CMOS: DNA computing