Reliability of Nanoscale Circuits and Systems

This book is intended to give a general overview of reliability, faults, fault models, nanotechnology, nanodevices, fault-tolerant architectures and reliability evaluation techniques. Additionally, the book provides an in depth state-of-the-art research results and methods for fault tolerance as well as the methodology for designing fault-tolerant systems out of highly unreliable components.

Includes supplementary material: sn.pub/extras

Auteur
Milo Stanisavljevic received the M.S. degree in electrical engineering from the Faculty of Electrical Engineering, University of Belgrade, Belgrade, Serbia, in 2004, and the Ph.D. degree in electrical engineering from the Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland, in 2009. During 2004, he was an Analog Design and Layout Engineer for Elsys Design, Belgrade/ Texas Instruments, Nice. In the end of 2004, he joined Microelectronic Systems Laboratory, EPFL, as a Research Assistant. During 2006, he was with International Business Machines Corporation (IBM) Research, Zurich, for six months, where he was involved in the project related to reliability emulation in the state-of-the-art nanoscale CMOS technology. He is currently engaged in the field of reliability and fault-tolerant design of nanometer-scale systems. His current research interests include mixed-signal gate and system level design, reliability evaluation, and optimization. Dr. Stanisavljevic received a Scholarship for Students with Extraordinary Results Awarded by the Serbian Ministry of Education from 1996 to 2004. Alexandre Schmid received the M.S. degree in Microengineering and the Ph.D. degree in Electrical Engineering from the Swiss Federal Institute of Technology (EPFL) in 1994 and 2000, respectively. He has been with the EPFL since 1994, working at the Integrated Systems Laboratory as a research and teaching assistant, and at the Electronics Laboratories as a post-doctoral fellow. He joined the Microelectronic Systems Laboratory in 2002 as a Senior Research Associate, where he has been conducting research in the fields of non-conventional signal processing hardware, nanoelectronic reliability, bioelectronic and brain-machine interfaces. Dr. Schmid has published over 70 peer-reviewed journal and conference papers. He has served in the conference committee of The International Conference on Nano-Networks since 2006, as technical program chair in 2008, and general chair in 2009.Dr. Schmid is an Associate Editor of the IEICE ELEX. Dr. Schmid is also teaching at the Microengineering and Electrical Engineering Departments/Sections of EPFL. Yusuf Leblebici received his B.Sc. and M.Sc. degrees in electrical engineering from Istanbul Technical University, in 1984 and in 1986, respectively, and his Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign (UIUC) in 1990. Between 1991 and 2001, he worked as a faculty member at UIUC, at Istanbul Technical University, and at Worcester Polytechnic Institute (WPI). In 2000-2001, he also served as the Microelectronics Program Coordinator at Sabanci University. Since 2002, Dr. Leblebici has been a Chair Professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), and director of Microelectronic Systems Laboratory. His research interests include design of high-speed CMOS digital and mixed-signal integrated circuits, computer-aided design of VLSI systems, intelligent sensor interfaces, modeling and simulation of semiconductor devices, and VLSI reliability analysis. He is the coauthor of 4 textbooks, namely, Hot-Carrier Reliability of MOS VLSI Circuits (Kluwer Academic Publishers, 1993), CMOS Digital Integrated Circuits: Analysis and Design (McGraw Hill, 1st Edition 1996, 2nd Edition 1998, 3rd Edition 2002), CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications (Springer, 2007) and Fundamentals of High Frequency CMOS Analog Integrated Circuits (Cambridge University Press, 2009), as well as more than 200 articles published in various journals and conferences. He has served as an Associate Editor of IEEE Transactions on Circuits and Systems (II), and IEEE Transactions on Very Large Scale Integrated (VLSI) Systems. He has also served as the general co-chair of the 2006 European Solid-State Circuits Conference, and the 2006 European Solid State Device Research Conference (ESSCIRC/ESSDERC). He is a Fellow of IEEE and has been elected as Distinguished Lecturer of the IEEE Circuits and Systems Society for 2010-2011.

Texte du rabat
Reliability of Nanoscale Circuits and Systems: Methodologies and Circuit Architectures Milos Stanisavljevic Alexandre Schmid Yusuf Leblebici Future integrated circuits are expected to be made of emerging nanodevices and their associated interconnects, but the reliability of such components is a major threat to the design of future integrated computing systems. Reliability of Nanoscale Circuits and Systems: Methodologies and Circuit Architectures confronts that challenge. The first part discusses the state-of-the-art of the circuits and systems as well as the architectures and methodologies focusing the enhancement of the reliability of digital integrated circuits. It proposes circuit and system level solutions to overcome high defect density and presents reliability, fault models and fault tolerance. It includes an overview of nano-technologies that are considered in the fabrication of future integrated circuits and covers solutions provided in the early ages of CMOs as well as recent techniques. The second part of the text analyzes original circuit and system level solutions. It details an architecture suitable for circuit-level and gate-level redundant modules implementation and exhibiting significant immunity to permanent and random failures as well as unwanted fluctuation and the fabrication parameters. It also proposes a novel general method enabling the introduction of fault-tolerance and evaluation of the circuit and architecture reliability. And the third part proposes a new methodology that introduces reliability in existing design flows. That methodology consists of partitioning the full system to design into reliability optimal partitions and applying reliability evaluation and optimization at local and system level.

Contenu
Introduction.- Reliability, Faults and Fault Models.- Nanotechnology and Nanodevices.- Fault-Tolerant Architectures and Approaches.- Reliability Evaluation Techniques.- Averaging Design Implementations.- Statistical Evaluation of Fault-Tolerance Using Proability Density Functions.- System Level Reliability Evaluation and Optimization.- Summary and Conclusions.- References.