Versatile Hardware Analysis Techniques

This book describes several versatile hardware analysis techniques that tackle existing and new challenges. These techniques cover different phases of the hardware development process, including the verification, debugging, and post-synthesis optimization phases. The authors introduce the Waveform Analysis Language (WAL), which allows users to code analysis tasks in the form of programs that run on waveforms. The book covers processor verification, formal microcode verification, programmable automated waveform analysis demonstrated for a large variety of previously manual analysis tasks, as well as netlist optimization leveraging formal methods. All methods are available as open source, typically include examples on RISC-V analysis problems, providing a strong foundation for the community.

Introduces automated waveform analysis based on a DSL to execute programs on waveforms Includes practical examples for waveform analysis including demonstrations for RISC-V processors Presents novel approaches for processor verification, microcode verification & netlist optimization with formal methods

Auteur

Lucas Klemmer received the M.Sc. degree in computer science from the University of Bremen, Germany, in 2020. Afterwards, he started as a PhD student with the Institute for Complex Systems, Johannes Kepler University Linz, Austria and received his PhD in computer science in 2024. He is currently working as a Postdoc at the same institute. He published several papers at international conferences and journals, such as ASP-DAC, DATE, DAC, FDL, and TCAD. His current research interests include RISC-V, the waveform-based analysis of hardware designs, and novel applications for formal methods in the verification and synthesis domains. He received the Best Paper Award at FDL 2022 and the JKU Young Researchers' Award for his PhD thesis in 2024.

Daniel Große received the Dr.-Ing. Degree in computer science from the University of Bremen in 2008. He remained as a Post-Doctoral Researcher with the Group of Computer Architecture, University of Bremen. In 2010, he was a substitute Professor for computer architecture with the University of Freiburg, Germany. From 2013 to 2014, he was the CEO of the EDA start-up solvertec focusing on automated debugging techniques. After that, until 2020, he was a Senior Researcher at the University of Bremen as well as Scientific Coordinator of the Graduate School System Design funded within the German Excellence Initiative. In addition, he has been working at the German Research Center for Artificial Intelligence (DFKI) since 2015. In July 2020, he became a full professor at the Johannes Kepler University Linz, Austria, where he is the head of the Institute for Complex Systems as well as the head of the "LIT Secure and Correct Systems Lab" (composing the expertise of over ten JKU institutes) since 2022. His current research interests include verification, virtual prototyping, debugging, synthesis and RISC-V. He published over 170 papers in peer-reviewed journals and conferences in the above areas. Dr. Große served in program committees of numerous conferences, including ASP-DAC, DAC, DATE, ICCAD, CODES+ISSS, GLSVLSI, FDL, ETS, and MEMOCODE and was the General Chair of FDL 2022. He received best paper awards (FDL 2007, DVCon Europe 2018, ICCAD 2018, FDL 2020 and FDL 2022) as well as business-related awards (IKT Innovativ Award 2013, Weconomy Award 2013, and Embedded Award 2014). He is an IEEE Senior Member and an Allied Member of the Accellera Systems Initiative in the SystemC Verification Working Group.

Contenu

Chapter 1 Introduction.- Chapter 2 Background.- Chapter 3 Processor Verification by Equivalent Program Execution.- Chapter 4 A Formally Verified Microcoded RISC-V Platform.- Chapter 5 The Waveform Analysis Language.- Chapter 6 Programmable Analysis of RISC-V Processors using WAL.- Chapter 7 HDL-Integrated Waveform Analysis.- Chapter 8 An Interactive Debugging Methodology Based on WAL.- Chapter 9 Netlist Optimization using Formal Methods under ExternalConstraints.- Chapter 10 Conclusion and Outlook.