Matching Properties of Deep Sub-Micron MOS Transistors

Matching Properties of Deep Sub-Micron MOS Transistors examines this interesting phenomenon. Microscopic fluctuations cause stochastic parameter fluctuations that affect the accuracy of the MOSFET. For analog circuits this determines the trade-off between speed, power, accuracy and yield. Furthermore, due to the down-scaling of device dimensions, transistor mismatch has an increasing impact on digital circuits. The matching properties of MOSFETs are studied at several levels of abstraction:

A simple and physics-based model is presented that accurately describes the mismatch in the drain current. The model is illustrated by dimensioning the unit current cell of a current-steering D/A converter.

The most commonly used methods to extract the matching properties of a technology are bench-marked with respect to model accuracy, measurement accuracy and speed, and physical contents of the extracted parameters.

The physical origins of microscopic fluctuations and how they affect MOSFET operation are investigated. This leads to a refinement of the generally applied 1/area law. In addition, the analysis of simple transistor models highlights the physical mechanisms that dominate the fluctuations in the drain current and transconductance.

The impact of process parameters on the matching properties is discussed.

The impact of gate line-edge roughness is investigated, which is considered to be one of the roadblocks to the further down-scaling of the MOS transistor.

Matching Properties of Deep Sub-Micron MOS Transistors is aimed at device physicists, characterization engineers, technology designers, circuit designers, or anybody else interested in the stochastic properties of the MOSFET.

Aimed at device physicists, characterization engineers, technology designers, circuit designers, or anybody else interested in the stochastic properties of the MOSFET Includes supplementary material: sn.pub/extras

Texte du rabat

Matching Properties of Deep Sub-Micron MOS Transistors examines this interesting phenomenon. Microscopic fluctuations cause stochastic parameter fluctuations that affect the accuracy of the MOSFET. For analog circuits this determines the trade-off between speed, power, accuracy and yield. Furthermore, due to the down-scaling of device dimensions, transistor mismatch has an increasing impact on digital circuits. The matching properties of MOSFETs are studied at several levels of abstraction: A simple and physics-based model is presented that accurately describes the mismatch in the drain current. The model is illustrated by dimensioning the unit current cell of a current-steering D/A converter. The most commonly used methods to extract the matching properties of a technology are bench-marked with respect to model accuracy, measurement accuracy and speed, and physical contents of the extracted parameters. The physical origins of microscopic fluctuations and how they affect MOSFET operation are investigated. This leads to a refinement of the generally applied 1/area law. In addition, the analysis of simple transistor models highlights the physical mechanisms that dominate the fluctuations in the drain current and transconductance. The impact of process parameters on the matching properties is discussed. The impact of gate line-edge roughness is investigated, which is considered to be one of the roadblocks to the further down-scaling of the MOS transistor. Matching Properties of Deep Sub-Micron MOS Transistors is aimed at device physicists, characterization engineers, technology designers, circuit designers, or anybody else interested in the stochastic properties of the MOSFET.

Résumé

Matching Properties of Deep Sub-Micron MOS Transistors examines this interesting phenomenon. Microscopic fluctuations cause stochastic parameter fluctuations that affect the accuracy of the MOSFET. For analog circuits this determines the trade-off between speed, power, accuracy and yield. Furthermore, due to the down-scaling of device dimensions, transistor mismatch has an increasing impact on digital circuits. The matching properties of MOSFETs are studied at several levels of abstraction:

A simple and physics-based model is presented that accurately describes the mismatch in the drain current. The model is illustrated by dimensioning the unit current cell of a current-steering D/A converter.

The most commonly used methods to extract the matching properties of a technology are bench-marked with respect to model accuracy, measurement accuracy and speed, and physical contents of the extracted parameters.

The physical origins of microscopic fluctuations and how they affect MOSFET operation are investigated. This leads to a refinement of the generally applied 1/area law. In addition, the analysis of simple transistor models highlights the physical mechanisms that dominate the fluctuations in the drain current and transconductance.

The impact of process parameters on the matching properties is discussed.

The impact of gate line-edge roughness is investigated, which is considered to be one of the roadblocks to the further down-scaling of the MOS transistor.

Matching Properties of Deep Sub-Micron MOS Transistors is aimed at device physicists, characterization engineers, technology designers, circuit designers, or anybody else interested in the stochastic properties of the MOSFET.

Contenu

Introduction: Matching analysis. Importance for circuit design. State of the art. Research objectives. Outline of this book.- Measurement and Modeling of Mismatch. Measurement setup. Experimental setup. Modeling of mismatch in the drain current. Width and length dependence. Example: Yield of a current-steering D/A converter. Conclusions.- Parameter Extraction. Extraction methods. Experimental setup. Comparison of extraction methods. Future issues. Conclusions.- Physical Origins of Mosfet Mismatch. Basic operation of the MOS transistor. Mismatch in the drain current. Physical origins of fluctuations. Conclusions.- Technological Aspects. Technology descriptions. Impact of the gate. Impact of the halo implantation. Comparison of di®erent CMOS technologies. Alternative device concepts. Conclusions.- Impact of Line-Edge Roughness. Characterization of line-edge roughness. Modeling the impact of line-width roughness. Experimental investigation of the impact of LWR. Prediction of the impact of LWR and guidelines. Conclusions.- Conclusions, Future Work and Outlook. Conclusions. Future work.- Outlook.