VHDL Primer, A

Auteur

J. Bhasker (Ph.D., University of Minnesota) is a member of the Technical Staff at AT&T Bell Laboratories, Allentown, PA, where he is currently working on a high-level synthesis tool that would synthesize net-lists from C or VHDL behavioral descriptions. He teaches courses on VHDL and VHDL Synthesis to internal AT&T designers as well as at Lehigh University. He is the author of A VHDL Primer (Prentice Hall) and numerous professional papers and articles. Dr. Bhasker has served as Program Committee member and session chair for the VHDL International Users Forum and was the recipient of the Honeywell Excel Pioneer Award (1987).

Texte du rabat

The power of VHDL-without the complexity!

Want to leverage VHDL's remarkable power without bogging down in its notorious complexity? Get A VHDL Primer, Third Edition. This up-to-the-minute introduction to VHDL focuses on the features you need to get results-with extensive practical examples so you can start writing VHDL models immediately.

Written by Jayaram Bhasker, one of the world's leading VHDL course developers, this best-selling guide has been completely updated to reflect the popular IEEE STD_LOGIC_1164 package. With Bhasker's help, you'll master all these key VHDL techniques:

• Behavioral, dataflow and structural modeling.
• Generics and configurations.
• Subprograms and overloading.
• Packages and libraries.
• Model simulation.
• Advanced features: Entity statements, generate statements, aliases, guarded signals, attributes, aggregate targets, and more. The book's extensive hardware modeling coverage includes modeling of regular structures, delays, conditional operations, state machines, Moore and Mealy FSMs, clock dividers and much more. You'll find new coverage of text I/O and test benches, as well as complete listings of the IEEE TD_LOGIC_1164 package. J. Bhasker has helped tens of thousands of professionals master VHDL. With A VHDL Primer, Third Edition, it's your turn to succeed.

Résumé

The aim of this book continues to be the introduction of the VHDL language to the reader at the beginner's level. VHDL is a large and verbose language with many complex constructs that have complex semantic meanings and is initially difficult to understand (the US military requires VHDL for device designs, thus explains its popularity vs. other HDLs). The book presents a subset of VHDL consisting of commonly used features that make it both simple and easy to use.

Contenu

1. Introduction.

What Is VHDL? History. Capabilities. Hardware Abstraction.

2. A Tutorial.

Basic Terminology. Entity Declaration. Architecture Body. Configuration Declaration. Package Declaration. Package Body. Model Analysis. Simulation.

3. Basic Language Elements.

Identifiers. Data Objects. Data Types. Operators.

4. Behavioral Modeling.

Entity Declaration. Architecture Body. Process Statement. Variable Assignment Statement. Signal Assignment Statement. Wait Statement. If Statement. Case Statement. Null Statement. Loop Statement. Exit Statement. Next Statement. Assertion Statement. Report Statement. More on Signal Assignment Statement. Other Sequential Statements. Multiple Processes. Postponed Processes.

5. Dataflow Modeling.

Concurrent Signal Assignment Statement. Concurrent versus Sequential Signal Assignment. Delta Delay Revisited. Multiple Drivers. Conditional Signal Assignment Statement. Selected Signal Assignment Statement. The UNAFFECTED Value. Block Statement. Concurrent Assertion Statement. Value of a Signal.

6. Structural Modeling.

An Example. Component Declaration. Component Instantiation. Other Examples. Resolving Signal Values.

7. Generics and Configurations.

Generics. Why Configurations? Configuration Specification. Configuration Declaration. Default Rules. Conversion Functions. Direct Instantiation. Incremental Binding.

8. Subprograms and Overloading.

Subprograms. Subprogram Overloading. Operator Overloading. Signatures. Default Values for Parameters.

9. Packages and Libraries.

Package Declaration. Package Body. Design File. Design Libraries. Order of Analysis. Implicit Visibility. Explicit Visibility.

10. Advanced Features.

Entity Statements. Generate Statements. Aliases. Qualified Expressions. Type Conversions. Guarded Signals. Attributes. Aggregate Targets. More on Block Statements. Shared Variables. Groups. More on Ports.

11. Model Simulation.

Simulation. Writing a Test Bench. Converting Real and Integer to Time. Dumping Results into a Text File. Reading Vectors from a Text File. A Test Bench Example. Initializing a Memory. Variable File Names.

12. Hardware Modeling Examples.

Modeling Entity Interfaces. Modeling Simple Elements. Different Styles of Modeling. Modeling Regular Structures. Modeling Delays. Modeling Conditional Operations. Modeling Synchronous Logic. State Machine Modeling. Interacting State Machines. Modeling a Moore FSM. Modeling a Mealy FSM. A Generic Priority Encoder. A Simplified Blackjack Program. A Clock Divider. A Generic Binary Multiplier. A Pulse Counter. A Barrel Shifter. Hierarchy in Design.

Appendix A: Predefined Environment.

Reserved Words. Package STANDARD. Package TEXTIO.

Appendix B: Syntax Reference.

Conventions. The Syntax.

Appendix C: A Package Example.

The Package ATT_MVL.

Appendix D: Summary of Changes.

VHDL-93 Features. Portability from VHDL-87.

Appendix E: The STD_LOGIC_1164 Package.

Package STD_LOGIC_1164.

Appendix F: An Utility Package.

Package UTILS_PKG.

Bibliography.

Index. <B