Interconnect Technologies for Integrated Circuits and Flexible Electronics

This contributed book provides a thorough understanding of the basics along with detailed state-of-the-art emerging interconnect technologies for integrated circuit design and flexible electronics. It focuses on the investigation of advanced on-chip interconnects which match the current as well as future technology requirements. The contents focus on different aspects of interconnects such as material, physical characteristics, parasitic extraction, design, structure, modeling, machine learning, and neural network-based models for interconnects, signaling schemes, varying signal integrity performance analysis, variability, reliability aspects, associated electronic design automation tools. The book also explores interconnect technologies for flexible electronic systems. It also highlights the integration of sensors with stretchable interconnects to demonstrate the concept of a stretchable sensing network for wearable and flexible applications. This book is a useful guide for those working in academia and industry to understand the fundamentals and application of interconnect technologies.

Focuses on the investigation of advanced on-chip interconnects to match the current and future technology requirements Enriches understanding by including contributions from leading experts across the globe Broadens understanding of interconnect technologies for flexible electronic system

Auteur
Dr. Yash Agrawal is faculty at Dhirubhai Ambani Institute of Information and Communication Technology (DA-IICT) Gandhinagar, Gujarat, India. He has accomplished his Postdoc in network-on-chip design and graphene materials from University of Rennes, France. He graduated with his Ph.D. and M.Tech. degrees from the National Institute of Technology (NIT) Hamirpur, HP, India. He attained university rank from Nagpur University during his B.E. degree in Electronics and Communication in 2009. He achieved the third place in all India Mentor Graphics design contest held at Bangalore, India, in 2011. His research interest includes VLSI interconnects, EMC and signal integrity of high speed interconnects, optimization schemes, numerical method analysis, nanotechnology, network-on-chip designs, flexible electronics, FPGA based designs, image processing using VLSI architectures, VLSI design for bio-medical devices, etc. He has conductedvarious Government funded workshops and conferences. He has several publications in contributed books, journals, and various national and international conferences of repute. He has received IETE K. S. Krishnan Memorial Award for best system oriented paper in 2017. He is reviewer of various reputed journals. He is a member of IEEE and chair of IEEE SSC&ED societies, Gujarat section 2023.

Dr. Kavicharan Mummaneni received B.Tech degree in Electronics and Communication Engineering Department from JNTU Hyderabad, M.Tech degree in Electronics Design and Technology specialization from NIT Calicut and Ph.D in VLSI domain from NIT Warangal. Currently working as an Assistant Professor-I at National Institute of Technology Silchar. His research interests include: Microelectronic devices, VLSI interconnects, Signal Integrity, Power Integrity, Device Modelling, Carbon Nanotube Interconnects, Flexible electronic design. He has published several research papers and book chapters in the domain of Micro/Nanoelectronic devices and circuits. He is a Senior IEEE member and Fellow of IETE India.

Dr. P. Uma Sathyakam is working as Associate Professor in the School of Electrical Engineering, Vellore Institute of Technology, Vellore, where he earned his MS (by Research) in Nanoelectronics and VLSI in 2011 and his PhD in Nanoelectronics in 2018. Prior to this, he earned his BSc. Electronics from University of Kerala, Thiruvananthapuram in 2005 and MSc. Applied Electronics from Bharathiar University, Coimbatore with distinction and Gold medal in 2007.

He served as a Research Fellow in a MHRD sponsored project on 'Development of online Lab in Microelectronics and VLSI' at VIT. He was also a Research Associate during his MS at VIT. He has more than 13 years of teaching and research experience. His current research interests are nano-electrodes for supercapacitors, Plasmonics, VLSI interconnects, carbon nanotube electronics, graphene, electronic materials and renewable energy materials. He has authored three books and 25 papers in peer reviewed journals and conferences. He is an Associate Editor of Nanotechnology for Environmental Engineering, a Springer Nature journal. He is also a peer reviewer for many journals. He has reviewed more than 75 papers for journals from IEEE, Elsevier, Springer, IET, Nature, Taylor & Francis, Trans Tech Publishers, and Wiley. He is a Senior Member of IEEE EDS/EPS.

Contenu
Chapter 1. An Efficient Model Order Reduction of Interconnects using Machine Learning for Timing Analysis.- Chapter 2. Delay and Overshoot Modelling of Asymmetric T-Tree Interconnects.- Chapter 3. Explicit Power-Delay Models for On-chip Copper and SWCNT Bundle Interconnects.- Chapter 4. Modelling and Analysis of Copper and Carbon Nanotube VLSI Interconnects.- Chapter 6. Through Silicon Vias for 3D Integration A Mini Review.- Chapter 7. Neural Networks for Fast Design Space Exploration of On-chip Interconnect Networks.- Chapter 8. A Comprehensive Analysis of Emerging Variants of Swarm Intelligence for Circuits and Systems.- Chapter 9. PAM3: History, Algorithm, and Performance Comparison to NRZ, PAM4.- Chapter 10. Emerging Interconnect Technologies for Integrated Circuit and Flexible Electronics.- Chapter 11. Contact and Interconnect Considerations for Organic and Flexible Electronics.- Chapter 12. Stretchable Interconnects: Materials, Geometry, Fabrication and Applications.- Chapter 13. Flexible Electronics: A Critical Review.- Chapter 14. Delay Analysis of Different Stretchable Interconnect Structures.- Chapter 15. Flexible Sensors for Plant Disease Monitoring.- Chapter 16. GaitTracker: A Digital Platform for Measuring, Detecting and Analyzing Gait Changes.