Fundamentals of IP and SoC Security

This book is about security in embedded systems and it provides an authoritative reference to all aspects of security in system-on-chip (SoC) designs. The authors discuss issues ranging from security requirements in SoC designs, definition of architectures and design choices to enforce and validate security policies, and trade-offs and conflicts involving security, functionality, and debug requirements. Coverage also includes case studies from the trenches of current industrial practice in design, implementation, and validation of security-critical embedded systems. Provides an authoritative reference and summary of the current state-of-the-art in security for embedded systems, hardware IPs and SoC designs; Takes a "cross-cutting" view of security that interacts with different design and validation components such as architecture, implementation, verification, and debug, each enforcing unique trade-offs; Includes high-level overview, detailed analysis on implementation, and relevant case studies on design/verification/debug issues related to IP/SoC security.

Provides an authoritative reference and summary of the current state-of-the-art in security for embedded systems, hardware IPs and SoC designs; Takes a "cross-cutting" view of security that interacts with different design and validation components such as architecture, implementation, verification, and debug, each enforcing unique trade-offs; Includes high-level overview, detailed analysis on implementation, and relevant case studies on design/verification/debug issues related to IP/SoC security. Includes supplementary material: sn.pub/extras

Auteur
Swarup Bhunia received his B.E. (Hons.) from Jadavpur University, Kolkata, India, and the M.Tech. degree from the Indian Institute of Technology (IIT), Kharagpur. He received his Ph.D. from Purdue University, IN, USA, in 2005. Currently, Dr. Bhunia is a professor in the department of Electrical and Computer Engineering at University of Florida, Gainesville, FL, USA. Earlier, Dr. Bhunia has served as the T. and A. Schroeder associate professor of Electrical Engineering and Computer Science at Case Western Reserve University, Cleveland, OH, USA. He has over ten years of research and development experience with over 200 publications in peer-reviewed journals and premier conferences and four books (three edited) in the area of VLSI design, CAD and test techniques. His research interests include low power and robust design, hardware security and trust, adaptive nanocomputing and novel test methodologies. He has worked in the semiconductor industry on RTL synthesis, verification, andlow power design for about three years. Dr. Bhunia received IBM Faculty Award (2013), National Science Foundation (NSF) career development award (2011), Semiconductor Research Corporation (SRC) technical excellence award (2005), best paper award in International Conference on VLSI Design (VLSI Design 2012), best paper award in International Conference on Computer Design (ICCD 2004), best paper award in Latin American Test Workshop (LATW 2003), and best paper nomination in Asia and South Pacific Design Automation Conference (ASP-DAC 2006) and in Hardware Oriented Test and Security (HOST 2010), nomination for John S. Diekhoff Award, Case Western Reserve University (2010) and SRC Inventor Recognition Award (2009).
Sandip Ray is a Principal Engineer at NXP Semiconductors. His research primarily involves developing correct, dependable, secure, and trustworthy computing through cooperation of specification, synthesis, architecture and validation technologies. Before joining NXP, Dr. Ray was a Research Scientist at Strategic CAD Labs, Intel Corporation where he led the research on pre-silicon and post-silicon validation of security and functional correctness of Intel's next-generation SoC designs, design-for-security and design-for-debug architectures, CAD tools, and specifications for security assurance. Dr. Ray has over 60 publications in peer-reviewed premier international journals and conferences. He was a guest editor for an IEEE Transactions on Multi-Scale Systems (TMSCS) special issue on Wearables, Implants, and Internet-of-Things, as well as special issues of ACM Transactions on Design Automation of Electronic Systems (TODAES) and Springer Journal on Electronic Testing Theory and Applications (JETTA). His research has found applications in a number of companies, including AMD, Freescale, Galois, IBM, Intel, NXP, and Rockwell Collins. He has received several recognition awards from Intel for his extensive contribution in the field of securityarchitecture and validation. He has given invited, tutorial, and keynote presentations at several international forums on security, validation, and energy challenges in the IoT regime. Dr. Ray has served as a program committee member more than 40 international meetings and conferences, and as program chair for Formal Methods in Computer-Aided Design. He currently serves as an Associate Editor for IEEE TMSCS and Springer Journal on Hardware and Systems Security. He has a Ph.D. from University of Texas at Austin and is a Senior Member of IEEE.

Susmita Sur-Kolay received the B.Tech.(Hons.) degree in Electronics and Electrical Communications Engineering from Indian Institute of Technology Kharagpur and the Ph.D. degree in Computer Science and Engineering from Jadavpur University India. She has been a faculty member in the Advanced Computing and Microelectronics Unit of the Indian Statistical Institute, Kolkata, India since 1999 and is presently a Professor as well as the Professor-in-Charge of the Computer and Communication Sciences Division of the institute. During the period 1993-99, she was a Reader in the Department of Computer Science and Engineering of Jadavpur University. Prior to that, she was a post-doctoral fellow at University of Nebraska-Lincoln, and a Research Assistant at the Laboratory for Computer Science in Massachusetts Institute of Technology. She was also a Visiting Researcher at Princeton University and Visiting Faculty at Intel Corp., USA. Her research contributions are in the areas of electronic design automation for VLSI physical design, fault modeling and testing, hardware security, synthesis of quantum computers, and graph algorithms. She has several international research collaborations. She has co-edited two books, authored a book chapter in the Handbook of Algorithms for VLSI Physical Design Automation, and co-authored about 100 technical articles in leading international journals and refereed conference proceedings. She was the General Co-Chair of the 29th International Conference on VLSI Design (2016), Technical Program Co-Chair of the 18th International Conference on VLSI Design (2005), the 11th Symposium on VLSI Design and Test (2007), and ISVLSI 2011, and has served on the program committees of several international conferences. She has served on the editorial board of the IET Computers and Digital Techniques, and IEEE Transactions on VLSI Systems. She is a Distinguished Visitor of IEEE Computer Society (India), Senior Member of IEEE, Member of ACM, IET and VLSI Society of India. Among other awards, she was the recipient of the President of India Gold Medal (summa cum laude) at IIT Kharagpur (1980), IBM Faculty Award (2009).

Contenu
Introduction.- Security Validation.- SoC Security and Debug.- IP Trust: The Problem and Design/Validation based Solution.- Security of Crypto IP Core: Issues and Countermeasures.- PUF-Based Authentication.- FPGA-based IP and SoC Security.- Physical Unclonable Functions and Intellectual Property Protection Techniques.- A Systematic Approach to Fault-Attack Resistant Design.- Hardware Trojan Attacks and Countermeasures.- In-place Logic Obfuscation for Emerging Nonvolatile FPGAs.- Security Standards for Embedded Devices and Systems.- Conclusion.