Ultra-Low Energy Domain-Specific Instruction-Set Processors

This book presents a systematic methodology for exploiting word-width information in embedded compilers. It details a technique for a context-driven strength reduction for constant multiplications, including a trade-off with application accuracy requirements.

1. General overview and context

2. Global state-of-the-art overview

3. Energy consumption breakdown for embedded platform targets

4. High level embedded arch and compiler requirements

5. Overall architecture exploration framework

6. Clustered loop buffer and data cluster organisation

7. Multi-threading in uni-threaded processors

8. Indirectly addressed arrays and dynamic data structure handling on scratchpad memories

9. Asymmetric foreground memory organisation

10. Exploiting word-width information in the processor datapath

11. Advanced strength reduction in shift-add based operations

12. Bioimaging application demonstrator

Contenu
Global State-of-the-Art Overview.- Energy Consumption Breakdown and Requirements for an Embedded Platform.- Overall Framework for Exploration.- Clustered L0 (Loop) Buffer Organization and Combination with Data Clusters.- Multi-threading in Uni-threaded Processor.- Handling Irregular Indexed Arrays and Dynamically Accessed Data on Scratchpad Memory Organisations.- An Asymmetrical Register File: The VWR.- Exploiting Word-Width Information During Mapping.- Strength Reduction of Multipliers.- Bioimaging ASIP benchmark study.- Conclusions.