The Core Test Wrapper Handbook

In the early to mid-1990's while working at what was then Motorola Se- conductor, business changes forced my multi-hundred dollar microprocessor to become a tens-of-dollars embedded core. I ran into first hand the problem of trying to deliver what used to be a whole chip with something on the order of over 400 interconnect signals to a design team that was going to stuff it into a package with less than 220 signal pins and surround it with other logic. I also ran into the problem of delivering microprocessor specification verifi- tion a microprocessor is not just about the functions and instructions included with the instruction set, but also the MIPs rating at some given f- quency. I faced two dilemmas: one, I could not deliver functional vectors without significant development of off-core logic to deal with the reduced chip I/O map (and everybody's I/O map was going to be a little different); and two, the JTAG (1149. 1) boundary scan ring that was around my core when it was a chip was going to be woefully inadequate since it did not support - speed signal application and capture and independent use separate from my core. I considered the problem at length and came up with my own solution that was predominantly a separate non-JTAG scan test wrapper that supported at-speed application of launch-capture cycles using the system clock. But my problems weren't over at that point either.

Guides engineers through the process of building a 1500 wrapper Provides insight into the rules and recommendations of IEEE Std. 1500 Focus on practical design considerations inherent to the application of IEEE Std. 1500 by discussing design choices and other decisions relevant to this IEEE standard The authors provide background information about some of the choices and decisions made throughout the design of IEEE Std. 1500 Includes supplementary material: sn.pub/extras

Texte du rabat
* The Core Test Wrapper Handbook: Rationale and Application of IEEE Std. 1500TM

provides insight into the rules and recommendations of IEEE Std. 1500. The authors present background information about some of the choices and decisions made throughout the

design of this IEEE standard conceived to enable efficient core test reuse and debug at the

SOC level.

The Core Test Wrapper Handbook: Rationale and Application of IEEE Std. 1500TM focuses on practical design considerations and design choices inherent to the application of IEEE Std. 1500. This book teaches an engineer how to add a 1500 wrapper to their core in easy to understand steps. Starting with a bare core (a core without 1500 wrapper), the book progressively builds a 1500 compliant wrapper around this core while discussing overall requirements for each portion of the 1500 wrapper. The Core Test Wrapper Handbook: Rationale and Application of IEEE Std. 1500TM is a very valuable reference for professionals and researchers in the areas of design for test, design for test reuse/design reuse, and SOC implementation.

Résumé
In the early to mid-1990's while working at what was then Motorola Se- conductor, business changes forced my multi-hundred dollar microprocessor to become a tens-of-dollars embedded core. I ran into first hand the problem of trying to deliver what used to be a whole chip with something on the order of over 400 interconnect signals to a design team that was going to stuff it into a package with less than 220 signal pins and surround it with other logic. I also ran into the problem of delivering microprocessor specification verifi- tion a microprocessor is not just about the functions and instructions included with the instruction set, but also the MIPs rating at some given f- quency. I faced two dilemmas: one, I could not deliver functional vectors without significant development of off-core logic to deal with the reduced chip I/O map (and everybody's I/O map was going to be a little different); and two, the JTAG (1149. 1) boundary scan ring that was around my core when it was a chip was going to be woefully inadequate since it did not support - speed signal application and capture and independent use separate from my core. I considered the problem at length and came up with my own solution that was predominantly a separate non-JTAG scan test wrapper that supported at-speed application of launch-capture cycles using the system clock. But my problems weren't over at that point either.

Contenu
What is the IEEE 1500 Standard?.- Why use the IEEE 1500 Standard?.- Illustration Example.- Design of the IEEE 1500 Interface Port.- Instruction Types.- Design of the WBR.- Design of the WBY.- Design of the WIR.- Hierarchical Cores.- Finalizing the Wrapper Solution for the EX Core.- SOC Integration of 1500 Compliant Cores.