Variation Tolerant On-Chip Interconnects

This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects. Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems.

Provides comprehensive, circuit-level explanation of high-performance, energy-efficient, variation-tolerant on-chip interconnect Describes design techniques to mitigate problems caused by variation Includes techniques for design and implementation of self-timed on-chip interconnect, delay variation insensitive communication protocols, high speed signaling techniques and circuits, bit-width independent completion detection and process, voltage and temperature variation tolerance

Auteur
Introduction.- Interconnect Design Techniques.- On-Chip Wire Modeling.- Design of Delay-Insensitive Current Sensing Interconnects.- Enhancing Completion Detection Performance.- Energy Efficient Semi-Serial Interconnect.- Comparison of the Designed Interconnects.- Circuit Techniques for PVT Variation Tolerance.

Contenu
Introduction.- On-Chip Communication.- Interconnect Design Techniques.- Design of Delay-Insensitive Current Sensing Interconnects.- Enhancing Completion Detection Performance.- Energy Efficient Semi-Serial Interconnect.- Comparison of the Designed Interconnects.- Circuit Techniques for PVT Variation Tolerance.