Design Automation and Applications for Emerging Reconfigurable Nanotechnologies

This book is a single-source solution for anyone who is interested in exploring emerging reconfigurable nanotechnology at the circuit level. It lays down a solid foundation for circuits based on this technology having considered both manual as well as automated design flows. The authors discuss the entire design flow, consisting of both logic and physical synthesis for reconfigurable nanotechnology-based circuits. The authors describe how transistor reconfigurable properties can be exploited at the logic level to have a more efficient circuit design flow, as compared to conventional design flows suited for CMOS. Further, the book provides insights into hardware security features that can be intrinsically developed using the runtime reconfigurable features of this nanotechnology.

Details an entire design automation flow for building circuits based on emerging reconfigurable nanotechnology Describes logical abstraction for emerging reconfigurable nanotechnology that is essential for building newer circuits Presents hardware security solutions that use reconfigurable nanotechnology to complement contemporary CMOS circuits

Auteur
Shubham Rai is working as a Research Engineer at Robert Bosch Research Center, Renningen, Germany. He was working as a research associate in the group from Oct, 2016. He obtained his Ph.D. Degree (Dr. Ing.) from TU Dresden, Germany in 2022. He received his B.Engg. in Electrical and Electronics engineering and M.Sc. in Physics from Birla Institute of Technology and Science Pilani, India. From 2011 till 2016, he worked in an RnD role at Mentor Graphics (Now under Siemens group), Noida India. Then, he worked at Green IC group at NUS, Singapore as a research assistant for 5 months before coming to Germany. His research interests are HW-SW codesign, logic synthesis, hardware security, reconfigurable platforms. He is a member of the IEEE and of the ACM. He has received Best Paper award nominations at IWLS 2021, and ISVLSI 2020.

Akash Kumar is a chaired Professor of Processor Design (with tenure) in the department of Computer Science at Technische Universität Dresden (TUD), Germany. From 2009 to 2015, he was with the Department of Electrical and Computer Engineering, NUS. He received the joint Ph.D. degree in electrical engineering in embedded systems from Eindhoven University of Technology (TU/e) and National University of Singapore (NUS), in 2009; joint Master's degree from TU/e and NUS in 2005 in embedded systems and Bachelor of Computer Engineering degree from NUS in 2002.

His research interests span various aspects of design automation in the context of embedded real-time systems with particular emphasis on reliable, resource-efficient and predictable architectures for embedded systems, including FPGA-based architectures. His research spans across various layers in the system design from hardware design to application analysis. He has published close to 240 articles in premier international conferences and journals in the area of design automation. Together with his research group, he has released many open-source tool flows for system design and analysis to allow the community to reproduce their results and to further research in the related areas.

He serves (or has recently served) on the program committee of renowned conferences in the area like DAC, DATE, FPL and CASES. He was the program chair of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'18 and '19), Embedded Systems for Real-Time Multimedia (ESTIMedia '17), subcommittee chair for several editions of Design Automation and Test in Europe (DATE) conference and Brief Presentations Chair for Real-time Systems Symposium (RTSS'19) and Associate Editor for Elsevier Microprocessors and Microsystems journal for 2013-2017.

Contenu
Chapter 1 . Introduction.- Chapter 2 . Preliminaries.- Chapter 3 . Exploring Circuit Design Topologies for RFETs.- Chapter 4 . Standard Cells and Technology Mapping.- C hapter 5 . Logic Synthesis with XOR-Majority Graphs.- Chapter 6 . Physical synthesis flow and liberty generation.- Chapter 7 . Polymporphic Primitives for Hardware Security .- Chapter 8 . Conclusion.