High-K Dielectric MOSFETs Propelling Technological Evolution

Advances in high-k fabrication technology have enabled tremendous rates of progress in the microelectronics industry by both improving the performance of individual transistors and allowing more transistors to be integrated onto a chip. In years to come, MOS with high-k might be the one changing the scenarios on how small transistors can be made. Hence studies on this device should continue with intensive experimentation. The impact of high-k dielectric (TiO2) is also observed on NMOS transistor. The sub-threshold leakage current is found to be decreased with increasing threshold voltage; this reduces the power consumption and thus improves the NMOS transistor performance. The reduction in gate leakage and sub-threshold swing projects the high-k NMOS structure to be a strong alternative for future Nanoscale MOS devices. It can also be concluded from the analysis that as devices are scaled down, the threshold voltage decreases.

Auteur

La Dra. Puja Acharya es profesora adjunta en la Universidad K. R. Mangalam. Ella ha hecho B.Tech, M.Tech y Ph.D (Antena Diseño) en Electrónica e Ingeniería de Comunicaciones con más de 15 años de experiencia docente. sus áreas de interés en la robótica integrada, comunicación óptica, Antena Diseño y Micro Electrónica.